From: YunQiang Su Date: Sun, 18 Mar 2018 11:05:51 +0000 (+0100) Subject: Support MIPS release 6. X-Git-Tag: cln_1-3-5~48 X-Git-Url: https://www.ginac.de/CLN/cln.git//cln.git?a=commitdiff_plain;h=139bce44f67937aec7257b72c786e0c8b5e55314;p=cln.git Support MIPS release 6. MIPS release 6 is not full compatible with the previous releases, it removes some instructions and changes encoding of some instruction. the `multu' is included. MIPS r6 drops `lo' and `hi' registers, and then removes `multu'/`mfhi'/`mflo'. Instead it uses `mulu' to compute the low part and `muhu' to compute the high part. --- diff --git a/src/base/cl_low.h b/src/base/cl_low.h index c4c25ab..1262376 100644 --- a/src/base/cl_low.h +++ b/src/base/cl_low.h @@ -273,10 +273,15 @@ inline uint32 mulu32_unchecked (uint32 arg1, uint32 arg2) unused (hi_zuweisung _hi); lo_zuweisung _lo; \ }) #elif defined(__GNUC__) && defined(__mips__) && !defined(NO_ASM) + #if __mips_isa_rev >= 6 + #define MULTU_HI_LO "mulu %1,%3,%2 ; muhu %0,%3,%2" + #else + #define MULTU_HI_LO "multu %3,%2 ; mfhi %0 ; mflo %1" + #endif #define mulu32(x,y,hi_zuweisung,lo_zuweisung) \ ({ var register uint32 _hi; \ var register uint32 _lo; \ - __asm__("multu %3,%2 ; mfhi %0 ; mflo %1" \ + __asm__(MULTU_HI_LO \ : "=r" (_hi), "=r" (_lo) \ : "r" ((uint32)(x)), "r" ((uint32)(y)) \ ); \ diff --git a/src/base/digitseq/cl_asm_mips_.cc b/src/base/digitseq/cl_asm_mips_.cc index f91244b..068b27a 100644 --- a/src/base/digitseq/cl_asm_mips_.cc +++ b/src/base/digitseq/cl_asm_mips_.cc @@ -88,9 +88,14 @@ DECLARE_FUNCTION(mulu32_) .ent mulu32_ // Input in $4,$5, Output in $2,mulu32_high mulu32_: +#if __mips_isa_rev >= 6 + mulu $2,$5,$4 // arg1 * arg2, lo + muhu $6,$5,$4 // arg1 * arg2, hi +#else multu $5,$4 // arg1 * arg2 mfhi $6 // hi mflo $2 // lo +#endif sw $6,mulu32_high // hi abspeichern // Adressierung?? Deklaration?? j $31 // return .end mulu32_